Journal
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS
Volume 8, Issue 1, Pages 206-214Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JESTPE.2019.2944167
Keywords
Silicon carbide; MOSFET; Lattices; Temperature dependence; Transient analysis; Silicon; Metals; Avalanche capability; failure mechanism; melting of metal system; numerical simulation; SiC MOSFET; unclamped inductive switching (UIS)
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This article focuses on the avalanche energy handing ability and theoretical demonstration of the avalanche failure mechanism for the SiC MOSFET by the unclamped inductive switching (UIS) test, the mathematical model, and the numerical simulation. Two evaluation methods are implemented to understand the effect of the avalanche current density and the avalanche energy on the device failure with the ambient temperature ranging from 300 to 450 K. Moreover, the thermodynamic model based on the thermal diffusion equation is developed to explore the critical temperature limitation. The avalanche capability highly depends on the dimension parameters and premature degradation points. The numerical simulation with the multicells and the real device parameters is used to reveal the electric performances of the SiC MOSFET during the UIS for the first time. At the same time, the temperatures in the SiC lattice and the metal system are precisely separated by the numerical method. The experimental results and simulation study demonstrate that the molten metal system on the surface of the SiC MOSFET induced by the local high temperature is prone to generate the thermal stresses and damage the device during the UIS transient. This failure mechanism is perfectly supported by the experimental, modeling, and numerical results.
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