Journal
JAPANESE JOURNAL OF APPLIED PHYSICS
Volume 59, Issue -, Pages -Publisher
IOP PUBLISHING LTD
DOI: 10.35848/1347-4065/ab6862
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- JSPS KAKENHI [JP18KK0134]
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Metal-oxide-semiconductor (MOS) capacitors with various gate dielectrics were fabricated on (111) oriented n-type 3C-SiC. Deposited SiO2 by sputtering without an interlayer (IL) and thermally grown SiO2 show deteriorated capacitance-voltage (C-V) characteristics and high interface trap density (D-it) over 10(11)-10(12) cm(-2) eV(-1). By inserting an IL, C-V and leakage current characteristics are improved. In particular, an atomic layer deposited (ALD) Al2O3-IL is suitable for 3C-SiC, which successfully achieved low D-it in the order of 10(10) cm(-2) eV(-1). MOS capacitor with the same gate dielectric on n-Si shows contradictory characteristics. Structural analysis shows it is considered the flat and uniform interface at Al2O3/3C-SiC leads good electrical characteristics. The 3C-SiC MOS capacitor with Al2O3-IL showed slightly negative flatband voltage and it is induced by negative interfacial dipole generated at the Al2O3/3C-SiC interface. This 3C-SiC MOS structure can be fabricated at low process temperature (<600 degrees C), which means the overall process for device application can be designed more flexibly. (C) 2020 The Japan Society of Applied Physics
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