4.8 Article

Subtraction-Mode Switched-Capacitor Converters With Parasitic Loss Reduction

Journal

IEEE TRANSACTIONS ON POWER ELECTRONICS
Volume 35, Issue 2, Pages 1200-1204

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TPEL.2019.2933623

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Funding

  1. Research Grants Council of the Theme-Based Research Scheme of Hong Kong [T23-612/12-R]

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In this letter, subtraction-mode switched-capacitor (SC) converters are proposed and analyzed. When compared to a conventional summation-mode SC converter, some of the flying capacitors of the subtraction-mode SC converters have reduced voltage swings, and hence the switching loss of the corresponding positive- and negative-plate parasitic capacitors is reduced, and efficiency is enhanced. The proposed subtraction-mode topologies use the same number of flying capacitors and switches as the summation-mode topologies, and they are reconfigured without using any auxiliary circuits, so there are no tradeoffs in terms of power density, cost, voltage conversion ratio (VCR), or equivalent output resistance. A test chip with VCRs of 1/3x, 2/3x, 3/4x, and 4/5x was fabricated in a 65-nm CMOS process. Efficiency improvement of more than 10% was achieved when compared to summation-mode designs.

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