Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 67, Issue 1, Pages 383-388Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2019.2956781
Keywords
CMOS integrated circuits; FET; metal-induced gap states (MIGSs); tungsten diselenide (WSe)
Funding
- NNetRA Program of MeitY
- Department of Science and Technology (DST)
- Ministry of Human Resource Development (MHRD), Government of India
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For semiconductor industry to replace silicon CMOS integrated circuits by 2-D semiconductors or transition metal dichalcogenides (TMDs), TMD-based n-FETs as well as p-FETs having performance better than Si FETs are a must. While a lot of literature demonstrates n-channel characteristics, the major roadblocks in the realization of TMD-based CMOS integrated circuit are the lack of approach to realize p-channel transistors having performance comparable to n-channel transistors, all realized over the same TMD substrate. To address this, we propose a new technique by engineering WSe2/metal interface to realize WSe2-based high-performance p- and n-channel transistors and therefore unveil its potential toward CMOS-integrated technology. The technique involves a dry process, based on the chemistry between the sulfur atom and WSe2 surface, that induces unique metal-induced gap states in the source/drain (S/D) contact area, which causes improved hole (electron) injection when Cr (Ni) as S/D metal was used. This has enabled the controlled realization of high-performance WSe2 FETs with desired polarity (N, P, or ambipolar), which solely depends on the contact metal used and contact engineering (CE)/surface engineering. Fundamental investigations on the effect of the proposed CE on metal-WSe2 interface revealed interesting and counter-intuitive facts, which very well corroborate with experimental observations.
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