Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume 67, Issue 1, Pages 212-224Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSI.2019.2948791
Keywords
Approximate computing; distributed arithmetic; inner-product computation; probabilistic analysis; energy efficient designs
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Funding
- Department of Science and Technology, Government of India [CRG/2018/002919]
- TEOCO Chair of Indian Institute of Technology Gandhinagar, Gujarat, India
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Distributed arithmetic (DA)-based approximate structures are used for efficient implementation of inner-products in various error-resilient applications. In the existing literature, most of these approximate architectures are developed by truncating the least significant bits (LSBs) of the inputs and/or the multiplying coefficients. The existing works do not provide any analytical study to evaluate and design an approximate structure. To address this issue, an analytical framework is proposed in this paper. It is shown that the analytical results match very closely with the Monte Carlo simulation results. The proposed framework reveals that the truncation of the LSBs of partial inner-products is a promising alternative to design more efficient DA architectures with less error. Following these observations, a novel approach to truncate the LSBs of partial inner-products, namely, a weight-dependent truncation strategy and its two variants with a suitable error compensation function are presented in this paper. Synthesis results, accuracy analysis, and evaluation in two commonly used error-tolerant applications demonstrate the superiority of the proposed architectures over the state-of-the-art DA-based approximate structures.
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