Induced Start Dynamic Sampling for Wafer Metrology Optimization

Metrology, which plays an important role in ensuring production quality in modern manufacturing industries, incurs substantial costs both in terms of the infrastructure required and the time needed to perform measurements. In particular, in the semiconductor manufacturing industry, measuring fundamental quantities on different sites of a wafer surface is associated with increased production time. To increase metrology efficiency, a typical strategy is to limit the number of sites measured and to exploit statistical models (soft sensing) to reconstruct the wafer profile. Moreover, for quality reasons, spatial dynamic sampling strategies may be employed to ensure that all regions of a wafer surface are checked periodically during production. In this paper, we propose a new sampling strategy, called induced start dynamic sampling (ISDS), which adapts greedy feature selection algorithms to the spatial dynamic sampling problem, such that the number of measured sites at each process run is minimized while achieving good wafer profile reconstruction accuracy and process visibility. The superiority of the proposed strategy with respect to the state of the art is demonstrated using both simulated data and an industrial chemical vapor deposition case study. Note to Practitioners-In this paper, we tackle a practical metrology problem encountered in semiconductor manufacturing, namely, the design of a dynamic wafer measurement plan to monitor the accuracy of a process across the whole wafer surface. The measurement plan is called dynamic, since the measurement locations, which are drawn from a candidate set that provides coverage of the whole wafer, change at each process iteration. Our methodology addresses the challenge of finding an optimized tradeoff between the number of measurements performed on each wafer and the reconstruction accuracy that can be achieved for the unmeasured areas on the wafer while, at the same time, for quality assurance purposes, ensuring that all locations on a wafer are visited in a finite number of process runs. The major benefit of the methodology is that it can significantly reduce the number of sites that need to be measured on each wafer enabling greater throughput on metrology tools without sacrificing process monitoring and anomaly detection capability.