Journal
ELECTRONICS LETTERS
Volume 56, Issue 9, Pages 424-425Publisher
INST ENGINEERING TECHNOLOGY-IET
DOI: 10.1049/el.2019.4105
Keywords
timing jitter; positron emission tomography; readout electronics; time-digital conversion; avalanche photodiodes; photodetectors; biomedical electronics; CMOS logic circuits; LSB; CMOS; single photon avalanche diode array; Vernier ring-oscillator-based time-to-digital converter; prelogic circuit; power consumption; TDC; position emission tomography single photon avalanche diode based detectors; RMS jitter Vernier time-to-digital converter; RMS timing jitter; dynamic range; electronic readout; time 5; 5 ps; time 5; 1 ps; time 4; 0 ns; power 22; 0 muW; size 65; 0 nm
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Funding
- Natural Sciences and Engineering Research Council of Canada (NSERC)
- Fonds de recherche du Quebec - Nature et technologies (FRQNT)
- Vanier Canada Graduate Scholarships
- CMC Microsystems
- Canada Research Chair tier-1 on time-of-flight positron emission tomography
- Arthur B. McDonald Canadian Astroparticle Physics Research Institute
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A Vernier ring-oscillator-based time-to-digital converter (TDC) with a new prelogic is presented. Experimental results show that the proposed architecture achieve a 5.5 ps RMS timing jitter with a 5.1 ps LSB within an area of $0.00151\,{\rm mm}<^>2$0.00151mm2. Thanks to the new prelogic circuit, the power consumption of the circuit was optimised to $22\,{\rm \mu }{\rm W}$22 mu W at a rate of 1 Mevents/s for a dynamic range of 4 ns. The area, timing jitter and power consumption make the TDC suitable for an array of electronic readout in a position emission tomography single photon avalanche diode based detectors.
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