Journal
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT
Volume 68, Issue 11, Pages 4205-4221Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TIM.2019.2938436
Keywords
Field programmable gate arrays; Clocks; Delay lines; Taxonomy; Bibliographies; Signal resolution; Propagation delay; Field-programmable gate arrays (FPGAs); survey; time-interval measurement; time-to-digital converter (TDC)
Funding
- Fundacao para a Ciencia e Tecnologia (FCT)
- Bosch Car Multimedia through the Advanced Engineering Systems for Industry (AESI) Doctoral Program [PDE/BDE/114562/2016]
- FCT [UID/CEC/00319/2019]
- Fundação para a Ciência e a Tecnologia [PDE/BDE/114562/2016] Funding Source: FCT
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Over the past few years, the gap between field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) performance levels has been narrowed due to the constant development of FPGA technology. The high performance, together with the lower development costs and a shorter time to market, turns FPGA-based platforms attractive for a huge range of applications, among them time-to-digital converters (TDCs). It is, therefore, important to analyze the evolution of FPGA-based TDCs to better understand where the research efforts should be focused in the near future. This article presents and discusses the improvements on the FPGA-based TDC research, aiming to be a starting point for new studies on this field, with some guidelines for future research. A state-of-the-art literature review on the FPGA-based TDC is presented, aiming to categorize and discuss the existing architectures. This discussion addresses architectures' characteristics, limitations, and areas of application.
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