Journal
ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS
Volume 18, Issue 5, Pages -Publisher
ASSOC COMPUTING MACHINERY
DOI: 10.1145/3358182
Keywords
High-level synthesis; approximate computing; worst-case execution time; design space exploration
Funding
- Coordenacao de Aperfeicoamento de Pessoal de Nivel Superior - Brasil (CAPES) [001]
- Fundacao de Amparo a Pesquisa do Estado do Rio Grande do Sul (FAPERGS)
- Conselho Nacional de Desenvolvimento Cientifico e Tecnologico (CNPq)
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The adoption of High-Level Synthesis (HLS) has increased as the latest HLS tools have evolved to provide high-quality results while improving productivity and time-to-market. Concurrently, many works have been proposing the incorporation of approximate computing techniques within HLS toolchains, allowing automated generation of inexact circuits for error-tolerant application domains with the aim of trading-off computation accuracy with area/power savings or performance improvements. Thus, when attempting to make a design meet timing requirements, designers of real-time systems using HLS may resort to approximation approaches. However, current approximate HLS tools do not allow specifying real-time constraints, being instead error-constrained to explore area, power, or performance optimizations. In this work, we propose an approximate HLS framework for real-time systems that can be integrated with state-of-the-art HLS tools. With this framework designers can specify real-time constraints and satisfy them while minimizing the output error. It uses scheduling information and Worst-Case Execution Time (WCET) analysis for iteratively exploring time-error trade-offs of approximations in the time-critical execution path. Experimental results on signal and image processing benchmarks show that we can reduce the WCET of exact designs by up to 35% with acceptable quality degradation.
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