Journal
IET CIRCUITS DEVICES & SYSTEMS
Volume 13, Issue 8, Pages 1152-1159Publisher
INST ENGINEERING TECHNOLOGY-IET
DOI: 10.1049/iet-cds.2018.5564
Keywords
low-power electronics; SRAM chips; CMOS memory circuits; encoding; integrated circuit design; energy-efficient design; low-power input data encoding; data bit reordering algorithm; SRAM array; SRAM cells; energy consumption; low-power data decoding circuit; write read operations; static random access memory design; standard SRAM; low-power data encoding-decoding; power consumption; multiplexers; inverters; complementary metal oxide semiconductor technology; Lenna test image
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This study presents a new energy-efficient design for static random access memory (SRAM) using a low-power input data encoding and output data decoding stages. A data bit reordering algorithm is applied to the input data to increase the number of 0s that are going to be written into the SRAM array. Using SRAM cells which are more energy-efficient in writing a '0' than a '1' benefits from this, resulting in a reduction in the total power and energy consumptions of the whole memory. The input data encoding is performed using a simple circuit, which is built of multiplexers and inverters. After the read operation, data will be returned back to its initial form using a low-power data decoding circuit. Simulation results in an industrial and a predictive CMOS technology show that the proposed design for SRAM reduces the energy consumption of read and write operations considerably for some standard test images as input data to the memory. For instance, in writing pixels of Lenna test image into this SRAM and reading them back, 15 and 20% savings are observed for the energy consumption of write and read operations, respectively, compared with the normal write and read operations in standard SRAMs.
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