Analysis and Modeling of SiC JFET Bi-Directional Switches Parasitic Oscillation

Silicon carbide (SiC) junction field-effect transistor (JFET) based bi-directional switches (BDSs) have great potential in the construction of several power electronic circuits, including matrix converters, multi-level converters, solid state breakers, and so on. Parasitic oscillation in SiC JFET-based BDSs has direct impact on the stability and reliability of these circuits. Proper handling of parasitic oscillation becomes highly critical. This paper focuses on the parasitic oscillation suppression in SiC JFET-based BDSs. A parallel snubber capacitor or a series ferrite ring was often used to damp parasitic oscillation in switching circuits in the literature. However, conventionally, the snubber capacitance was obtained by time-consuming and labour-intensive trial-and-error methods. The main contribution of this study is to derive the simplified equivalent transient circuit of the SiC JFET-based BDS considering all parasitic elements and quantitatively define the reasonable range of the snubber capacitance. And the combined effect of the selected snubber capacitance and the selected ferrite ring is investigated. In the end, simulation and experimental results validate the effectiveness of the proposed method.