An Extended Study on an Interference-Insensitive Switched Capacitor CDC

A new Switched Capacitor (SC) Capacitance-to-Digital Converter (CDC) is presented in this paper. Its output exhibits a high-level of insensitivity to interference, by virtue of the conversion mechanism itself. The proposed scheme is a combination of an SC relaxation oscillator and an integrating type analog-to-digital converter (ADC). Its conversion time is independent of the measurand and hence can be set, such that it is an integral multiple of the interference period, unlike in a dual-slope ADC where the de-integration time is a function of the measurand. The final output is proportional to the number of transitions in the oscillator output, which is directly proportional to the value of the sensor capacitance and has negligible sensitivity to the presence of the interference signal. The proposed scheme has been realized and tested as a hardware prototype unit. The non-linearity of the scheme was found to be 0.4%, and the resolution, in terms of the effective number of bits (ENOB), was 11.13, when tested, with sensor capacitance varied from 10 to 32.5 pF. The studies conducted to evaluate the effect of capacitively coupled interference to the sensitive node on the CDC showed that it is negligible for a wide range of magnitude.