Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 54, Issue 9, Pages 2501-2512Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2019.2918940
Keywords
Digital phase-locked loop (DPLL); jitter; reference spur; ring digitally controlled oscillator (DCO); time-to-digital converter (TDC)
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Funding
- Samsung Research Funding Center of Samsung Electronics [SRFC-IT1702-02]
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This paper presents a ring-type, digitally controlled oscillator (DCO)-based integer-N digital phase-locked loop (DPLL) that can achieve low jitter and low reference spur concurrently. In order to minimize the quantization error, while consuming a small amount of power, this work presents an optimal-threshold (OT) time-to-digital converter (TDC). The thresholds of the OT TPC and the phase-correction gain of the loop are corrected continuously in the background. The PLL was fabricated in a 65-nm CMOS process and its measured rms jitter integrated from 1 kHz to 100 MHz and the reference spur of a 2.4-GHz frequency were 320 fs and -75 dBc, respectively. Through measurement, they were verified to be maintained robustly over temperature and supply variations. The active area was 0.055 mm(2), and the power consumption was 6.0 mW.
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