Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 54, Issue 9, Pages 2532-2542Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2019.2926648
Keywords
Analog to digital converter (ADC); current-domain; current-mode residue processing; gm-cell; open-loop amplifier; pipelined-successive-approximation register (SAR); split current digital-to-analog converter (DAC)
Categories
Ask authors/readers for more resources
This paper introduces a current-mode residue processing technique in a pipelined-successive-approximation register (SAR) analog-to-digital converter (ADC), which extends the operation speed of a single-channel ADC utilizing low-impedance-based signaling. A 10-bit pipelined-SAR ADC with featured building blocks such as a degenerated gm-cell as an open-loop residue amplifier, a switched-current mirror for sample-and-hold (S/H) function, and a split current digital-to-analog converter (DAC) for current-domain SAR conversion achieves a 500-MS/s conversion-rate under a 1.0-V supply. With background inter-stage mismatch calibration, a prototype ADC fabricated in a 28-nm CMOS process achieves 56.6-dB signal-to-noise-and-distortion ratio (SNDR) at a Nyquist input, resulting in a Walden figure of merit (FoM) of a 21.7-fJ/conversion-step.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available