Journal
IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS
Volume 25, Issue 5, Pages -Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSTQE.2019.2918930
Keywords
Avalanche photodiode (APD); backside etching; backside illumination (BSI); blue; buried oxide (BOX); CMOS image sensor; detector; electronic photonic integration; Geiger-mode avalanche photodiode (G-APD); high-volume manufacturing; integrated optics device; integration of photonics in standard CMOS technology; near infrared (NIR); near ultraviolet (NUV); optical sensing; optical sensor; photodetector; photodiode; photomultiplier; photon counting; photon timing; RGB-D sensor; semiconductor; sensor; silicon; silicon on insulator (SOI); single-photon avalanche diode (SPAD); single-photon imaging; standard CMOS technology; uniformity
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Funding
- Swiss National Science Foundation [166289]
- KIST Institutional Program of Flagship [2E29390]
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We present the world's first backside-illuminated (BSI) single-photon avalanche diode (SPAD) based on standard silicon-on-insulator (SOI) complementary metal-oxidesemiconductor (CMOS) technology. This SPAD achieves a good dark count rate (DCR) after backside etching, comparable to DCRs of BSI SPADs fabricated on bulk wafers. Unlike bulk-wafer-based BSI SPADs, which typically suffer from poor violet and blue sensitivity, the proposed BSI SPAD features increased near-ultraviolet sensitivity as well as significant sensitivity in the violet and blue spectral ranges, thanks to the ultrathin-body SOI. To the best of our knowledge, this is the best result ever reported for any BSI SPAD in the standard CMOS technology. In addition, it also shows high sensitivity at long wavelengths thanks to the interface between silicon and silicon-dioxide layers. Therefore, it achieves a photon detection probability over 26% at 500 nm and 10% in the 400-875 nm wavelength range at 3 V excess bias voltage. The timing jitter is 119 ps full width at half maximum at the same operation condition at 637 nm wavelength. For the proposed BSI SPAD, the buried oxide layer in SOI wafers is used as an etching stop during the wafer backside-etching process, and therefore it ensures the excellent performance uniformity in large arrays.
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