Journal
IEEE DESIGN & TEST
Volume 36, Issue 3, Pages 39-45Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/MDAT.2019.2902094
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Funding
- NSFC [61674094, 61720106013]
- NSF Expedition
- SRC Center (LEAST)
- SRC Center (ASCENT)
- SRC Center (CRISP)
- BNRist
- Beijing Innovation Center for Future Chips
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Editor's note: This article explores the design of high-density, low-power, and high-speed embedded nonvolatile memory arrays exploiting the unique device characteristics of the emerging ferroelectric FETs.
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