4.7 Article

All-2D ReS2 transistors with split gates for logic circuitry

Journal

SCIENTIFIC REPORTS
Volume 9, Issue -, Pages -

Publisher

NATURE PUBLISHING GROUP
DOI: 10.1038/s41598-019-46730-7

Keywords

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Funding

  1. National Research Foundation of Korea Grant - Korean Government [2017R1A5A1014862, 2018M3D1A1058793]
  2. National Research Foundation of Korea(NRF) - Ministry of Science, ICT & Future Planning [NRF2017R1A2B2006568]
  3. KU-KIST School Project
  4. National Research Foundation of Korea [2018M3D1A1058793, 2017R1A5A1014862] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)

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Two-dimensional (2D) semiconductors, such as transition metal dichalcogenides (TMDs) and black phosphorus, are the most promising channel materials for future electronics because of their unique electrical properties. Even though a number of 2D-materials-based logic devices have been demonstrated to date, most of them are a combination of more than two unit devices. If logic devices can be realized in a single channel, it would be advantageous for higher integration and functionality. In this study we report high-performance van der Waals heterostructure (vdW) ReS2 transistors with graphene electrodes on atomically flat hBN, and demonstrate a NAND gate comprising a single ReS2 transistor with split gates. Highly sensitive electrostatic doping of ReS2 enables fabrication of gate-tunable NAND logic gates, which cannot be achieved in bulk semiconductor materials because of the absence of gate tunability. The vdW heterostructure NAND gate comprising a single transistor paves a novel way to realize all-2D circuitry for flexible and transparent electronic applications.

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