Journal
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
Volume 47, Issue 8, Pages 1370-1380Publisher
WILEY
DOI: 10.1002/cta.2665
Keywords
clock jitter; continuous-time delta-sigma modulator (CT-DSM); current-steering DAC; excess loop delay (ELD); mismatch; nonreturn-to-zero (NRZ); return-to-zero (RZ)
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Funding
- Ministry of Science and ICT (MSIT), Korea, under the Information Technology Research Center (ITRC) support program [IITP-2019-2018-0-01421]
- Ministry of Trade, Industry Energy (MOTIE) [10080488]
- Korea Semiconductor Research Consortium (KSRC)
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This letter presents a 4-bit continuous-time delta-sigma modulator (CT-DSM) fabricated using a 65-nm CMOS process. The circuit is designed for wide-bandwidth applications, such as those related to wireless communications. This CT-DSM has an oversampling ratio of 16 with a 640-MHz sampling frequency. To reduce the clock jitter sensitivity and excess loop delay effect, the first DAC pulse is a nonreturn-to-zero (NRZ)-type pulse, whereas the second DAC pulse is a return-to-zero (RZ)-type pulse; this is accomplished using a current-steering DAC. In order to reduce mismatch without using a data-weighted averaging circuit, the size and layout of the unit current source in the current-steering DAC are considered carefully. The CT-DSM achieves a signal-to-noise ratio (SNR) of 67.3 dB, a signal-to-noise and distortion ratio (SNDR) of 63.4 dB, and a dynamic range of 75 dB for a 20-MHz signal bandwidth.
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