Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 66, Issue 6, Pages 2563-2568Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2019.2912618
Keywords
III-V; Fermi-level pinning; FinFETs
Funding
- Defense Threat Reduction Agency (DTRA) [HDTRA1-14-1-0057]
- Lam Research
- National Science Foundation (NSF) (E3S STC) [0939514]
- Korea Institute of Science and Technology
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We study the impact of fin-width scaling on transport in highly doped InGaAs fins and the effect of digital etch (DE). Our experiments suggest the existence of a 10-nm-wide deadzone on each side of the fin that does not contribute to the transport. The extent of the deadzone cannot be mitigated by DE nor sidewall passivation. Simulations suggest that the Fermi-level pinning and its associated subsurface depletion region alone cannot explain the relatively wide deadzone that is measured. We propose an explanation based on the combination of Fermi-level pinning and mobility degradation as the fin width scales down. This leads to an apparent wider deadzone than accounted by the Fermi-level pinning alone.
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