Four stage OTA CMOS frequency compensation based on double differential feedback paths

Multi-stage amplifiers become logical choices for high-speed electronics and data conversion. The main difficulty in design is performing frequency compensation due to increasing high impedance nodes. In this work, a four-stage CMOS amplifier is frequency compensated using double differential feedbacks paths. Only two small compensation capacitors, less than 1 pF are used to form four Miller loops and driving a 500 pF load capacitor. The transfer function is calculated and simplified to estimate circuit dynamics while HSPICE and TSMC 0.18 mu m CMOS technology are used to simulate the proposed four-stage amplifier. According to simulations and mathematical description, the proposed structure shows 147 dB, 6.3 MHz and 85 degrees as DC gain, GBW, and PM respectively while consumes 380 mu W as power dissipation. According to the defined figure of merits, the proposed circuit shows performance excellency against the previous state of art designs.