4.7 Article

25 x 50 Gbps wavelength division multiplexing silicon photonics receiver chip based on a silicon nanowire-arrayed waveguide grating

Journal

PHOTONICS RESEARCH
Volume 7, Issue 6, Pages 659-663

Publisher

OPTICAL SOC AMER
DOI: 10.1364/PRJ.7.000659

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Funding

  1. National Key Research and Development Program of China [2017YFA0206404]
  2. National Natural Science Foundation of China (NSFC) [61435013, 61534005, 61604146]

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A high-performance monolithic integrated wavelength division multiplexing silicon (Si) photonics receiver chip is fabricated on a silicon-on-insulator platform. The receiver chip has a 25 -channel Si nanowire-arrayed waveguide grating, and each channel is integrated with a high-speed waveguide Ge-on-Si photodetector. The central wavelength, optical insertion loss, and cross talk of the array waveguide grating are 1550.6 nm, 5-8 dB, and 12--15 dB, respectively. The photodetectors show low dark current density of 16.9 mA/cm(2) at -1 V and a high responsivity of 0.82 A/W at 1550 nm. High bandwidths of 23 and 29 GHz are achieved at 0 and - 1 V, respectively. Each channel can operate at 50 Gbps with low input optical power even under zero bias, which realizes an aggregate data rate of 1.25 Tbps. (C) 2019 Chinese Laser Press

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