4.8 Article

Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing

Journal

SCIENCE
Volume 364, Issue 6440, Pages 570-+

Publisher

AMER ASSOC ADVANCEMENT SCIENCE
DOI: 10.1126/science.aaw5581

Keywords

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Funding

  1. Sandia's Laboratory-Directed Research and Development (LDRD) Program under the Hardware Acceleration of Adaptive Neural Algorithms (HAANA) Grand Challenge
  2. Nanostructures for Electrical Energy Storage (NEES-II), an Energy Frontier Research Center - U.S. Department of Energy, Office of Science, Basic Energy Sciences [DESC0001160]
  3. U.S. Department of Energy's National Nuclear Security Administration [DE-NA-0003525]
  4. National Science Foundation
  5. Semiconductor Research Corporation, E2CDA [1739795]
  6. Stanford Graduate Fellowship fund
  7. Knut and Alice Wallenberg Foundation [KAW 2016.0494]
  8. National Science Foundation, National Nanotechnology Coordinated Infrastructure [ECCS-1542152]

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Neuromorphic computers could overcome efficiency bottlenecks inherent to conventional computing through parallel programming and readout of artificial neural network weights in a crossbar memory array. However, selective and linear weight updates and <10-nanoampere read currents are required for learning that surpasses conventional computing efficiency. We introduce an ionic floating-gate memory array based on a polymer redox transistor connected to a conductive-bridge memory (CBM). Selective and linear programming of a redox transistor array is executed in parallel by overcoming the bridging threshold voltage of the CBMs. Synaptic weight readout with currents <10 nanoamperes is achieved by diluting the conductive polymer with an insulator to decrease the conductance. The redox transistors endure >1 billion write-read operations and support >1-megahertz write-read frequencies.

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