High-Volume Testing and DC Offset Trimming Technique of On-Die Bandgap Voltage Reference for SOCs and Microprocessors

Since the VLSI chips were invented, as predicted by Moore's law, the performance, the power, and the cost of the VLSI chips have been improved, which brought a significant benefit to the economy. However, some of the analog circuits do not get a full benefit from the scaling, due to the increased device variability with transistors in smaller dimension. Under such circumstance, the calibration and trimming techniques are essential to overcome the sensitivity to the process variation. This paper presents the trimming technique to correct the direct current (dc) offset error of the bandgap voltage reference circuit, which complies with the high-volume manufacturing (HVM) requirements. The proposed trimming method consists of the combination of two different sequences, the coarse and fine trimming. The accuracy of the dc offset trimming is evaluated by the newly invented method that complies with the HVM requirements. With a compact silicon area of only 700 mu m(2), the dc offset trimming circuit achieved an accuracy of +/- 5 mV (4 sigma) as a result of the coarse and fine trimming operations.