Journal
IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS
Volume 13, Issue 2, Pages 271-281Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TBCAS.2019.2894775
Keywords
Battery-less SoCs; data-flow architecture; energy-harvesting; NVM; ultra-low power
Funding
- NSF [1423113, 1422854]
- NSF NERC ASSIST Center [EEC-1160483]
- Direct For Computer & Info Scie & Enginr
- Division of Computing and Communication Foundations [1422854] Funding Source: National Science Foundation
- Division Of Computer and Network Systems
- Direct For Computer & Info Scie & Enginr [1423113] Funding Source: National Science Foundation
Ask authors/readers for more resources
Improving system lifetime and robustness is a key to advancing self-powered platforms for real world applications. A complete self-powered, battery-less, wearable platform requires a microwatt-power system-on-chip (SoC), operating reliably within this budget, capable of surviving long periods without charging, and recovering from power loss to its previous state. To meet these requirements, we designed a wireless sensing heterogeneous system-in-package (SiP) containing an ultra-low power (ULP) SoC, a non-volatile boot memory (NVM), and a 2.4 GHz frequency shift key (FSK) radio, all integrated with custom ULP interfaces. The SoC includes a fully integrated energy harvesting platform power manager (EH-PPM) to power the SiP and other commercial sensors. The EH-PPM is designed for small loads and powers the SoC and peripherals while drawing very low operating current. The SoC also includes a digital system data-flow for sensing applications, an analog front end for ECG signal acquisition, and a cold-boot management system (CBMS) for boot and recovery from the NVM. The CBMS enables integration of the SoC with the ULP NVM to create a wearable form factor, self-powered system capable of recovery from power loss. The SoC also includes a radio interface tightly integrated with a compression accelerator to efficiently communicate with the FSK transmitter and reduce the FSK's transmission time. This tight integration between accelerators on the SoC and peripherals is another feature that reduces the system's power consumption by reducing the code size and number of memory accesses required to perform an operation. The SoC consumes 507 nW average power while running free-fall detection, 519 nW average power while measuring ambient temperature, and 1.02 mu W during continuous ECG monitoring and post-processing.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available