A 2.4-GHz Reference-Sampling Phase-Locked Loop That Simultaneously Achieves Low-Noise and Low-Spur Performance

Dividerless synthesizers such as sub-sampling phase-locked loops (PLLs) and injection-locked clock multipliers have demonstrated some of the lowest jitters for a given power consumption (jitter-power FoM j metric). However, they contain a tradeoff between the spur and noise performance, where techniques incorporated for spur reduction adversely affect jitter or power performance. A new dividerless Type-I sampling PLL, called the reference sampling PLL (RS-PLL), which estimates the voltage-controlled oscillator (VCO) phase error by sampling the reference sine wave with a VCO square wave is demonstrated. A clock-and-isolation buffer which accelerates the VCO sine wave to a square wave sampling clock and simultaneously isolates the VCO tank from spur mechanisms in the sampler is included in place of a traditional reference buffer. By combining sampling clock buffer and VCO isolation functionalities into a single block, the RS-PLL eliminates the noise penalty of two separate buffers. The power penalty due to sampling at VCO frequency is restricted by limiting the activity of the switching circuits to the region around the reference zero crossing where the phase error information exists. The prototype RS-PLL implemented in 65-nm CMOS achieves a jitter-power FoMi of <-251 dB between 2.05 and 2.55 CHz with a reference spur of <-66 dBc at 50 MHz. In doing so, it improves upon the simultaneous noise and spur performance achieved by current state-of-the-art clock multipliers.