Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 54, Issue 4, Pages 1161-1172Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2018.2888872
Keywords
Analog-to-digital converter (ADC); data weighting average; dynamic element matching (DEM); high linearity; incremental ADC (IADC); linear-exponential accumulation; mismatch error; multi-bit; notch; sigma delta; two phase
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Funding
- Science and Technology Development Fund, Macau [055/2012/A2]
- Research Committee of University of Macau [MYRG2017-00192-FST]
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This paper presents an incremental analog-to-digital converter (IADC) with a two-phase linear-exponential accumulation loop. In the linear phase, the loop works as a first-order structure. The noise-coupling (NC) path is then enabled in the exponential phase thus boosting the signal-to-quantization-noise ratio (SQNR) exponentially with a few number of clock cycles. The two-phase scheme combines the advantages of the thermal noise suppression in the first-order IADC and SQNR boosting in the exponential mode. The uniform-exponential weight function allows the data weighted averaging (DWA) technique to work well, leading to the rotation of the multi-bit DAC mismatch error. Meanwhile, this scheme does not destroy the notches, which can be utilized to suppress the line noise. Implemented in 65-nm CMOS under 1.2-V supply, the analog-to-digital converter (ADC) achieves an signal-to-noise + distortion ratio (SNDR)/dynamic range (DR) of 100.8 dB/101.8 dB with 20-kHz bandwidth (BW), 550 mu W, and 0.134 mm(2), resulting in Walden/Schreier FoM(W)/FoM(S) of 153 fJ/176.4 dB, respectively. The differential and integral non-linearities are +0.27 LSB/-0.27 LSB and +0.84 LSB/-0.81 LSB, respectively.
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