Journal
IEEE ELECTRON DEVICE LETTERS
Volume 40, Issue 5, Pages 710-713Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2019.2908084
Keywords
HfO2-based FeFET; endurance degradation; midgap voltage; oxide charge trapping; interface trap generation
Categories
Funding
- National Natural Science Foundation of China [51702273, 61504115]
- Huxiang Young Talents Plan Support Project of HunanProvince [2018RS3087]
- Science and Technology Innovation Project of Hunan Province [2017XK2048]
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The mechanism of memory window (MW) degradation of Hf0.5Zr0.5O2-based ferroelectric field-effect transistors (FeFETs) with program/erase (P/E) cycling is investigated. First, the P/E cycling properties of the FeFETs are characterized at different cycling voltages. Then, the midgap voltage method is proposed to address the underlying drivers for the threshold voltage shift and MW degradation by separating the effects of oxide-trapped charges and interface-trapped charges. The mechanism for different threshold voltage evolutions between programed and erased states during P/E cycling is revealed. Moreover, the amount of MW degradation is nearly equal to the difference of midgap voltage shift values between programed and erased states, and the interface trap generation contributes to the midgap voltage shift.
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