4.2 Article

An Efficient Multiple Fault Detection Technique in Digital Microfluidic Biochips

Journal

IETE JOURNAL OF RESEARCH
Volume 67, Issue 6, Pages 899-912

Publisher

TAYLOR & FRANCIS LTD
DOI: 10.1080/03772063.2019.1571954

Keywords

Biochip; DMFB; Droplet; Fault detection; Fluidic constraints; LOC

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This paper presents an efficient fault detection mechanism for Digital Microfluidic Biochips (DMFBs) to identify faulty electrodes on a biochip array through test droplet routing and capacitive sensing. The proposed technique aims to ensure safe assay performance on a chip by identifying defective electrode positions or zones through boundary, row, and diagonal tests, even in complex scenarios. Evaluation of the approach considers various faulty environments.
The involvement of Digital Microfluidic Biochips (DMFBs) in the field of disease detection, automated drug discovery, on-chip DNA (Deoxyribonucleic acid) analysis has become well-accepted during last decades. Though trustworthiness of Digital Microfluidic Biochip system plays a vital role in point-of-care diagnosis, defective electrodes are the main reasons for various misleading assay performances. It also affects overall assay completion time; even it leads to discard a chip in the worst scenario. Hence, fault detection is a crucial need. In this paper, an efficient fault detection mechanism is formulated to identify multiple numbers of defective/faulty electrodes on an m x n biochip array, where m and n can be of any positive number. Test droplets are strategically routed throughout an arbitrary sized electrode array and capacitive sensing circuit is deployed to take decision about existence of faults. The basic idea of the proposed technique is to identify actual positions of faulty electrodes through boundary test, row test, and diagonal test. In some complicated cases, instead of finding exact faulty location(s), through an extended testing our proposed technique identifies faulty zone(s) (it is a bounded region where one or more defective electrodes reside) to ensure safe assay performance on a chip. A detailed study evaluates the proposed approach considering different faulty environments.

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