Journal
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume 27, Issue 3, Pages 601-610Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TVLSI.2018.2878841
Keywords
Analog-to-digital converters (ADC); analog design; bias temperature instability (BTI); compound exponential-Poisson distribution; integrated circuit (IC) simulation; metal-oxide-semiconductor field-effect transistor (MOSFET) scaling; random telegraph noise; random telegraph noise (RTN); time-dependent variability
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Advanced scaling and the introduction of new materials in the metal-oxide-semiconductor field-effect transistor (MOSFET) raise concerns about its reliability. Several degradation mechanisms, depending on operating conditions and time, can cause a significant change of the transistor parameters. The transistor area plays a large role when it comes to aging. In large-area MOSFETs, aging appears deterministic, while in small-area devices it is stochastic and convoluted with random telegraph noise. This is analogous to the time-zero random variability, which also reduces as the transistor gate area increases. The scope of this paper is to extend the knowledge of the time-dependent random variability as a function of MOSFET gate area scaling. The goal is to aid the designers in transistor sizing toward a more reliable design. As an example, the impact of time-dependent random variability is illustrated for an analog-to-digital converter.
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