Journal
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume 27, Issue 2, Pages 407-415Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TVLSI.2018.2879341
Keywords
High speed; low power; radiation-hardened SRAM; single-event-multiple-node upsets (SEMNUs); Ssingle-event upset (SEU)
Funding
- National Natural Science Foundation of China [61674002, 61474001]
- National Science and Technology Major Project [2017ZX01028-101-003]
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In this paper, a novel radiation-hardened 14-transistor SRAM bitcell with speed and power optimized [radiation-hardened with speed and power optimized (RSP)-14T] for space application is proposed. By circuit-and layout-level optimization design in a 65-nm CMOS technology, the 3-D TCAD mixed-mode simulation results show that the novel structure is provided with increased resilience to single-event upset as well as single-event-multiple-node upsets due to the charge sharing among OFF-transistors. Moreover, the HSPICE simulation results show that the write speed and power consumption of the proposed RSP-14T are improved by similar to 65% and similar to 50%, respectively, compared with those of the radiation hardened design (RHD)-12T memory cell.
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