4.6 Article

An Impact Ionization MOSFET With Reduced Breakdown Voltage Based on Back-Gate Misalignment

Journal

IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 66, Issue 2, Pages 868-875

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2018.2887168

Keywords

Avalanche breakdown; impact ionization; low power; MOSFET; misaligned gate; steep subthreshold slope

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In this paper, we propose a misaligned double-gate p-i-n impact ionization MOS (MIMOS) with a deliberate misalignment between the top and bottom gates. The presence of a misaligned bottom gate leads to band-to-band-tunneling of electrons at the source-intrinsic region interface and increases the number of carriers for impact ionization. The electric field redistribution provides a longer transport path for the carriers. Therefore, carriers gain higher kinetic energy, and the impact ionization rate is enhanced in the MIMOS. This results in a significantly lower avalanche breakdown voltage compared to conventional single-gate IMOS structure. Using calibrated 2-D simulations, we demonstrate that MIMOS exhibits a steep subthreshold slope (similar to 6 mV/dec) at a significantly low-supply voltage of (V-DS = 0.59 V), which is similar to 48% lower than that of the corresponding single-gate IMOS (V-DS = 1.15 V).

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