Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 54, Issue 2, Pages 428-440Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2018.2879955
Keywords
Analog-to-digital converter (ADC); coefficient scaling; continuous-time (CT) delta-sigma (Delta Sigma) ADC; excess loop delay compensation (ELDC); hybrid ADC; low-noise and high-speed comparator; passive noise shaping (NS); successive approximation register (SAR)
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Funding
- NSF [1254459, 1509767, 1527320]
- Directorate For Engineering
- Div Of Electrical, Commun & Cyber Sys [1254459] Funding Source: National Science Foundation
- Div Of Electrical, Commun & Cyber Sys
- Directorate For Engineering [1509767] Funding Source: National Science Foundation
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This paper presents a compact and power efficient third-order continuous-time (CT) delta-sigma (Delta Sigma) analog-todigital converter (ADC) with a single operational transconductance amplifier (OTA). A 4-bit second-order fully passive noise-shaping (NS) successive-approximation-register (SAR) ADC is employed as the quantizer while inherently provides two additional NS orders. Fabricated in 40-nm CMOS, the prototype occupies 0.029 mm(2) of active area and consumes 1.16 mW of power when clocked at 500-MHz sampling frequency. The proposed CT Delta Sigma ADC achieves a peak signal-to-noise-anddistortion ratio (SNDR) of 70.4 dB over 12.5-MHz bandwidth, yielding a Walden figure of merit (FoM) of 17 fJ/conversion-step.
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