Proposal for Capacitance Matching in Negative Capacitance Field-Effect Transistors

Negative-capacitance transistors use ferroelectric (FE) material in the gate-stack to improve the transistor performance. The extent of the improvement depends on the capacitance matching between the FE capacitance (C-fe) and the underlying MOS transistor (C-MOS). Since both CMOS and Cfe have strong non-linearity, it is difficult to achieve a good matching for the entire operating gate voltage range. In this letter, we discuss a new approach using multi-layer FE to engineer the shape of Cfe. The proposed method is validated using the TCAD simulation of negative-capacitance FDSOI transistor, and the results show that it leads to better sub-threshold swing as well as lower power supply V-dd compared with a prototype single-layer negative-capacitance field-effect transistor.