Journal
IEEE ELECTRON DEVICE LETTERS
Volume 40, Issue 2, Pages 295-298Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2018.2888486
Keywords
Atomic layer deposition; dielectric breakdown; GaN MOS-HEMT; recess gate; interface trap density
Categories
Funding
- China Postdoctoral Science Foundation [2017M622442]
- Technology Innovation Project of Hubei Province [2017AAA127]
- Hubei Province Postdoctoral Scientific and Technological Activities Funded Project [G28]
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In this letter, we report optimized transport properties in gate recessed enhancement-mode GaN MOS-HEMTs by incorporating silicon into atomic layer deposited gate dielectric HfO2. Compared with commonly used HfO2 gate dielectric, the interface trap density can be reduced by nearly an order of magnitude and the fixed oxide traps inside are reduced to almost half using the high-quality passivation of HfSiOx. The MOS-HEMTs based on HfSiOx exhibit a threshold voltage of 1.5 V, excellent subthreshold swing of 65 mV/dec, and a high on-off ratio of 3 x 10(10). The incorporation of silicon in HfO2 can also increase the dielectric breakdown property with maximum gate electric field of 2.85 MV/cm for a 10-year time-dependent gate dielectric breakdown lifetime, which is 36% higher than pure HfO2. The maximum breakdown voltage of HfSiOx MOS-HEMT is 742 V, which is 30% higher than HfO2 MOS-HEMT.
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