Improved reversed nested miller frequency compensation technique based on current comparator for three-stage amplifiers

This paper attempts to propose a newly modified method to improve the frequency compensation of three-stage operational trans-conductance amplifiers. In the topology of the new frequency compensation, a current comparator is placed on the feedback path, while the common node of Miller compensation capacitors, the feedforward path, is removed by eliminating the right-half plane zero. This tremendously improves the phase margin, stability, and gain band width product. Compared with other available frequency compensation methods, the newly proposed method manages to improve the figure of merits and lower power consumption while significantly decreasing the dimensions of capacitors in the compensation network. The superiority of the new method over other conventional methods for reversed nested Miller compensation has been examined by a three stage amplifier that has been designed and simulated through a 180nm standard library CMOS. The results indicate that the new amplifier has achieved a power consumption of 285 mu W, gain band width product of 14MHz, and phase margin of 86 degrees with 100pF capacitance load at the supply voltage of 1.8V.