The investigation of the unseen interrelationship of grain size, ionic defects, device physics and performance of perovskite solar cells

Controlling the phenomenological morphology effects on the performance of the perovskite solar cell (PSC) is a continuing concern due to its photo-physical complexity and the existing contrary reports. Distinguishing the effect of the formed electron and hole traps in the bulk and at surface/interfaces of the perovskite layer from their impact on the performance of the device can be beneficial in optimizing fabrication methods. Here, the transient AC and steady state DC measurements, and morphology characterizations confirm the variation of performance parameters with respect to grain boundaries growth. The device physics is uncovered with respect to the grain size (GS) of the perovskite layer employing the theoretical drift-diffusion framework incorporating the electronic and ionic contributions. The increase of open circuit voltage (V-oc) for devices with large GS can be associated to the density of defect states. The findings here suggest a more pronounced role of interfaces in efficiency enhancement of the PSCs with the emphasis on the impact of the hole transport layer (HTL)/perovskite layer interface which is also found to be accountable to the difference between the device internal voltage and the terminal voltage and minimizing this difference can lead to an enhancement of approximately 100 mV in V-oc. Additionally, the electron traps in the bulk of the perovskite layer play a distinguishable role in the reduction of V-oc for the device with the smallest GS. The ionic defect density is also estimated. Considering our results and previous reports, the performance of the PSC is remarkably dependent on the method of fabrication and the associated perovskite conversion mechanism, and not necessarily on GS. The results are expected to deliver important guidelines for the development of more efficient PSCs by further enhancement of the V-oc towards its thermodynamic limit of 1.32V, via creating optimal interfaces.