A Type-I Sub-Sampling PLL With a 100 x 100 μm2 Footprint and-255-dB FOM

A dual-loop LC-voltage-controlled oscillator (VCO)-based frequency synthesizer, composed of an all-digital frequency-locked loop (ADFLL) and a voltage-mode, type-I, sub-sampling phase-locked loop (SS-PLL), is presented. A compact SS phase detector is described which also acts as a loop filter (LF). Fabricated in a 65-nm CMOS process, the synthesizer occupies a small footprint of 100 x 100 mu m(,)(2) thanks to its compact LF and full integration underneath the VCO inductor. The synthesizer achieves the sub-200 fs of rms integrated jitter across its tuning range of 4.6-5.6 GHz while consuming no more than 1.1 mW of power. A peak figure-of-merit (FOM) of -255 dB at 5 GHz and an FOM of -254 dB across the tuning range are achieved. A reference spur of -64.1 dBc is measured with the PLL operating at 5 GHz.