Journal
JOURNAL OF COMPUTATIONAL ELECTRONICS
Volume 12, Issue 4, Pages 658-665Publisher
SPRINGER
DOI: 10.1007/s10825-013-0526-z
Keywords
Modeling and simulation; Leakage current; Gate oxides; Dielectric reliability; Dielectric breakdown; Non-volatile memory
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In this paper we present a comprehensive physical model that describes charge transport and degradation phenomena in high-k stacks. The physical mechanisms are modeled using a novel material-related approach that includes in a self-consistent fashion the charge transport (dominated by defect-assisted contribution), power dissipation and temperature increase, defect generation, and ion and vacancy diffusion and recombination. The physical properties of defects, which play a crucial role in determining the electrical behavior of the high-k stacks, depend on their atomistic configurations, as calculated using ab-initio methods. This simulation framework represents a powerful tool to interpret electrical characterization measurements. In addition, it can be used to optimize logic and memory device stacks thanks to its predictive statistical capabilities that allow reproducing gate current, threshold voltage increase and time to breakdown (TDDB) statistics. Simulation results performed using this simulation package are shown to reproduce accurately leakage current, Stress-Induced Leakage Current (SILC), threshold voltage shift observed during Positive Bias Temperature Instability (PBTI) stress, TDDB in various dielectric stacks.
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