Nanoscale Device Modeling and Circuit-Level Performance Projection of Top-Gated Graphene Nanoribbon Field-Effect Transistor for Digital Logic Gates

Graphene nanoribbons (GNRs) is one of the promising candidates that can push the current silicon-based technology beyond its limits. Narrow strips of graphene or nanoribbons can have bandgap, is semiconducting and most suitable for high speed digital applications. The paper demonstrates the potential integration of graphene nanoribbons field-effect transistor (GNRFET) into digital logic circuit through SPICE modeling. The design rules used for the top layer of GNRFET dimension are compatible with the 45-nm complementary metal-oxide-semiconductor (CMOS) process technology. The device model is based on the top-of-the-barrier ballistic device modeling approach. A major improvement to the model is the substitution of the Newton-Raphson iteration with a non-linear analytic polynomial. By having a shorter and simpler expression, the simulation time is made 40% faster without depending on a numerical solution to compute the channel potential. Hence, the computing cost is effectively reduced. Furthermore, the compact model is now portable and it can be transferred and simulated easily between multiple electronic design automation (EDA) platforms. The graphene nanostructure model is implemented as NOT, NAND, NOR gates, D flip-flop and 1-bit adder where their circuit performance are assessed and tabulated for wide range of parameter variations namely nanoribbon channel width. It is revealed through the investigation that the maximum drain current, energy-delay product (EDP), and power-delay product (PDP) of logic circuits are inversely proportional to the nanoribbon width.