Journal
ECS SOLID STATE LETTERS
Volume 4, Issue 7, Pages Q32-Q35Publisher
ELECTROCHEMICAL SOC INC
DOI: 10.1149/2.0041507ssl
Keywords
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Funding
- Chinese Academy of Sciences [XDA09020402]
- National Key Basic Research Program of China [2013CBA01900, 2010CB934300, 2011CBA00607, 2011CB932804]
- National Integrate Circuit Research Program of China [2009ZX02023-003]
- National Natural Science Foundation of China [61176122, 61106001, 61261160500, 61376006]
- Science and Technology Council of Shanghai [12nm0503701, 13DZ2295700, 12QA1403900, 13ZR1447200, 14ZR1447500]
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Applying a high power pulse (HPP) before the standard single box SET pulse accelerates the crystallization process and reduces the SET resistance of phase change memory (PCM) cells. The effects of HPP on SET resistance distribution are characterized and analyzed. Dual pulses SET method (D-SET) is proposed and compared with some conventional SET methods. The results gathered across a 16 Kbits block of a 64 Mbits PCM test chip in 40 nm CMOS process show that D-SET achieves the fastest SET speed, the narrowest SET resistance distribution and smallest drift coefficient with set time of 300 ns. (C) 2015 The Electrochemical Society. All rights reserved.
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