Journal
SOLID-STATE ELECTRONICS
Volume 91, Issue -, Pages 87-90Publisher
PERGAMON-ELSEVIER SCIENCE LTD
DOI: 10.1016/j.sse.2013.10.010
Keywords
Transistor; MoS2; Hysteresis
Funding
- Army Research Lab Director's Strategic Initiative (DSI) program on interfaces in stacked 2D atomic layered materials
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Thermal and hysteresis effects are studied for the first time in Al2O3 top-gated, CVD grown monolayer MoS2 field effect transistors (FETs). Stressing with an applied bias reversed the hysteresis rotation in the high temperature I-ds-V-gs transfer characteristics and this behavior, indicative of a multilevel trap model, was explained by charge carriers interacting with traps possibly at the MoS2/dielectric interface and within the CVD grown MoS2. High temperature FET characteristics measured up to 125 degrees C demonstrated pinch-off degradation and the influence of trapping/detrapping rates in both the top and bottom gate dielectric. This indicates the importance of maintaining oxide and interface quality for good FET performance. Published by Elsevier Ltd.
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