Journal
SOLID-STATE ELECTRONICS
Volume 53, Issue 10, Pages 1112-1115Publisher
PERGAMON-ELSEVIER SCIENCE LTD
DOI: 10.1016/j.sse.2009.06.004
Keywords
CMOS; Series resistance; Ultra-thin body (UTB); Silicon-on-insulator (SOI); Elevated source/drain; Transmission line model; Specific contact resistivity
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Optimization of the series resistance of silicide contact structure in ultra-thin body (UTB) silicon-on-insulator (SOI) MOSFET with elevated source/drain (S/D) is examined through theoretical analysis and 2-dimensional simulation. It is found that the optimum silicide/Si interface position, which exhibits lowest parasitic series resistance, can be located at inside of 501 layer under the surface as the effective contact length is scaled down further below 100 nm regime. The closed-form analytical expressions derived from modified transmission line model principle provide a guideline for optimum design of silicide thickness and contact parameters in self-aligned silicide technology. (C) 2009 Elsevier Ltd. All rights reserved.
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