Journal
SOLID-STATE ELECTRONICS
Volume 52, Issue 8, Pages 1115-1126Publisher
PERGAMON-ELSEVIER SCIENCE LTD
DOI: 10.1016/j.sse.2008.04.035
Keywords
silicon-on-insulator (SOI); fully depleted SOI MOSFETs; low-frequency noise; strain engineering; low-field mobility; contact etch stop layer (CESL); strained SOI (sSOI)
Ask authors/readers for more resources
Strain engineering based on either a global approach using high-mobility substrates or the implementation of so-called processing-induced stressors has become common practice for 90 nm and below CMOS technologies. Although the main goal is to improve the performance by increasing the drive current, other electrical parameters such as the threshold voltage, the multiplication current, the low frequency noise and the gate oxide quality in general may be influenced. This paper reviews the impact of different global and local strain engineering techniques on the gate stack quality and its reliability, including hot carrier performance, negative bias temperature instabilities, time dependent dielectric breakdown and radiation hardness. Recent insights will be discussed and the influence of different strain engineering approaches illustrated. (C) 2008 Elsevier Ltd. All rights reserved.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available