Si-nanowire CMOS inverter logic fabricated using gate-all-around (GAA) devices and top-down approach

We present the monolithic integration of gate-all-around (GAA) Si-nanowire FETs into CMOS logic using top-down approach. Inverters are chosen as the test vehicles for demonstration. Empirically optimized designs show sharp ON-OFF transitions with high voltage-gains (e.g., Delta V-OUT/Delta V-IN up to similar to 45) and symmetric pull-up and pull-down characteristics. The matching of the drive Currents of n- and p-MOSFETs is achieved using different number of nanowire channels for N- and P-MOS transistors. The inverter maintains its good transfer characteristics and noise margins for wide range Of V-DD tested down to 0.2 V. The detailed experimental characterization is discussed along with the electrical characteristics of the individual transistors comprising the inverter. The performances of the inverters are discussed vis-A-vis those reported in the literature using advanced non-classical device architectures such as Fin-FETs. The integration potential of GAA Si-nanowire transistors to realize CMOS circuit functionality using top-down approach is thus demonstrated. (C) 2008 Elsevier Ltd, All rights reserved.