High-performance poly-silicon TFTs with high-k Y2O3 gate dielectrics

In this paper, we describe a poly-Si thin-film transistor (TFT) incorporating a high-k Y2O3 gate dielectric for different annealing times. The high-k Y2O3 poly-Si TFT device annealed in O-2 gas for 60 min exhibited better electrical characteristics in terms of a high effective carrier mobility of 32.7 cm(2) V-1 s(-1), small subthreshold slope of 269 mV dec(-1), and high I-on/I-off current ratio of 1.83 x 10(7). This result is attributed to a smooth surface, structural relaxation, and a low trap-state density at the Y2O3/poly-Si interface after a long time thermal annealing. All of these results suggest that the 60 min annealed poly-Si Y2O3 TFT is a good candidate for high-performance low-temperature poly-Si TFTs.