The impact of line edge roughness on the stability of a FinFET SRAM

3D mixed-mode device-circuit simulation is presented to investigate the impact of line edge roughness (LER) on the stability of a FinFET SRAM. In this work, LER sequence is statistically generated by a Fourier analysis of the power spectrum of Gaussian autocorrelation function. The sensitivity of 20 nm FinFET SRAM of Read and Write static noise margins (SNM) to fin LER is evaluated. The results show that FinFET SRAM is more tolerant of disturbance in write operation than in read disturbance. The dependence of Read SNM on fin LER's root mean square (RMS) amplitude, fin thickness and supply voltage is also analyzed. Furthermore, methods to reduce the LER effect on the FinFET SRAM's read stability are introduced. Optimization of the cell ratio by a multiple-fin design, control of the access transistor's gate bias voltage and replacement of a 6T cell with an 8T cell are possible solutions to continue the scaling trend of SRAM in the nanoscale CMOS technology.