4.4 Article

Formation of Through Silicon Vias for Silicon Interposer in Wafer Level by Metal-Assisted Chemical Etching

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCPMT.2015.2443728

Keywords

Metal-assisted chemical etching (MaCE); silicon interposer; through silicon vias (TSVs)

Funding

  1. Division of Civil, Mechanical and Manufacturing Innovation through National Science Foundation [CMMI 1130876]
  2. Directorate For Engineering
  3. Div Of Civil, Mechanical, & Manufact Inn [1130876] Funding Source: National Science Foundation

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This paper reports a novel wet chemical etching method, referred to as uniform metal-assisted chemical etching (MaCE), for uniform hole formation in fabrication of through silicon vias (TSVs) on silicon (Si) interposer in wafer level. In MaCE, a layer of Au as catalyst is deposited on the photolithography-patterned Si surface. Uniform holes are formed by simply immersing the Au-loaded Si into a hydrofluoric acid-hydrogen peroxide aqueous solution. In a typical experiment, similar to 1 million holes are formed after MaCE for 4 h at room temperature over a 4-in Si wafer with a diameter of 28 mu m, a depth of 162 mu m, a pitch size of 80 mu m, and a sidewall roughness below 50 nm. The holes show high geometric uniformity in wafer level, with their depth in the range 159-164 mu m, the diameter in 27.1-29.7 mu m, and high verticality. Simultaneous etching of two wafers in the same batch is also demonstrated. The TSV etched by MaCE show compatibility with SiO2 deposition by plasma-enhanced chemical vapor deposition and copper filling by electroplating. The reported method provides an approach for manufacturing TSV on Si interposer with simple operation, high geometric uniformity, high throughput, and low cost.

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