Journal
IEEE COMPUTER ARCHITECTURE LETTERS
Volume 14, Issue 2, Pages 140-143Publisher
IEEE COMPUTER SOC
DOI: 10.1109/LCA.2015.2402435
Keywords
Memory architecture; random access memory; nonvolatile memory; phase change memory; SDRAM
Categories
Funding
- NSF [1218867, 1213052, 1409798]
- Department of Energy [DE - SC0005026]
- Division of Computing and Communication Foundations
- Direct For Computer & Info Scie & Enginr [1409798, 1500848] Funding Source: National Science Foundation
Ask authors/readers for more resources
In this letter, a flexible memory simulator - NVMain 2.0, is introduced to help the community for modeling not only commodity DRAMs but also emerging memory technologies, such as die-stacked DRAM caches, non-volatile memories (e.g., STT-RAM, PCRAM, and ReRAM) including multi-level cells (MLC), and hybrid non-volatile plus DRAM memory systems. Compared to existing memory simulators, NVMain 2.0 features a flexible user interface with compelling simulation speed and the capability of providing sub-array-level parallelism, fine-grained refresh, MLC and data encoder modeling, and distributed energy profiling.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available
Share Paper
