Journal
IEEE COMPUTER ARCHITECTURE LETTERS
Volume 14, Issue 2, Pages 127-131Publisher
IEEE COMPUTER SOC
DOI: 10.1109/LCA.2015.2434872
Keywords
DRAM memory; bitwise AND/OR; performance
Categories
Funding
- NSF [0953246, 1212962, 1320531]
- Intel Science and Tech. Center
- Samsung
- SRC
- Direct For Computer & Info Scie & Enginr
- Division of Computing and Communication Foundations [0953246] Funding Source: National Science Foundation
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Bitwise operations are an important component of modern day programming, and are used in a variety of applications such as databases. In this work, we propose a new and simple mechanism to implement bulk bitwise AND and OR operations in DRAM, which is faster and more efficient than existing mechanisms. Our mechanism exploits existing DRAM operation to perform a bitwise AND/OR of two DRAM rows completely within DRAM. The key idea is to simultaneously connect three cells to a bitline before the sense-amplification. By controlling the value of one of the cells, the sense amplifier forces the bitline to the bitwise AND or bitwise OR of the values of the other two cells. Our approach can improve the throughput of bulk bitwise AND/OR operations by 9.7X and reduce their energy consumption by 50.5.X. Since our approach exploits existing DRAM operation as much as possible, it requires negligible changes to DRAM logic. We evaluate our approach using a real-world implementation of a bit-vector based index for databases. Our mechanism improves the performance of commonly-used range queries by 30 percent on average.
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