4.8 Article

Graphene field effect transistor without an energy gap

Publisher

NATL ACAD SCIENCES
DOI: 10.1073/pnas.1305416110

Keywords

electron optics; finite-difference time domain; gate geometry engineering; graphene transistor

Funding

  1. Department of Energy Light-Material Interactions in Energy Conversion-Energy Frontier Research Center [DE-SC0001293]
  2. National Science Foundation [CMMI-1120890]
  3. Functional Engineered Nano Architectonics via the Microelectronics Advanced Research Corporation at University of California, Los Angeles [2009-NT-2048]
  4. World Class University programs through National Research Foundation (NRF) of Korea funded by Ministry of Education, Science and Technology (MEST) [R31-2008-000-10055-0]
  5. Nanomaterial Technology Development Program through the NRF of Korea funded by MEST [2012M3A7B4049807]
  6. MEST (Center for Advanced Soft Electronics) [2011-0031640]
  7. [QMMRC R11-2008-053-01002-0]

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Graphene is a room temperature ballistic electron conductor and also a very good thermal conductor. Thus, it has been regarded as an ideal material for postsilicon electronic applications. A major complication is that the relativistic massless electrons in pristine graphene exhibit unimpeded Klein tunneling penetration through gate potential barriers. Thus, previous efforts to realize a field effect transistor for logic applications have assumed that introduction of a band gap in graphene is a prerequisite. Unfortunately, extrinsic treatments designed to open a band gap seriously degrade device quality, yielding very low mobility and uncontrolled on/off current ratios. To solve this dilemma, we propose a gating mechanism that leads to a hundredfold enhancement in on/off transmittance ratio for normally incident electrons without any band gap engineering. Thus, our saw-shaped geometry gate potential (in place of the conventional bar-shaped geometry) leads to switching to an off state while retaining the ultrahigh electron mobility in the on state. In particular, we report that an on/off transmittance ratio of 130 is achievable for a sawtooth gate with a gate length of 80 nm. Our switching mechanism demonstrates that intrinsic graphene can be used in designing logic devices without serious alteration of the conventional field effect transistor architecture. This suggests a new variable for the optimization of the graphene-based device-geometry of the gate electrode.

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